One chip. Six cores. A shared world.
Explore the Intel Core i7-8700K reference platform and the educational simulator inspired by it.
Coffee Lake
Model scope and assumptions
Coffee Lake-inspired educational model; not a native x86 emulator.
Choose an example or open your saved recording. Files you open stay in this browser.
Recording summary ·
Summary covers every observed step, including before the replay window. Task duration is summed host work, not elapsed time, utilization or cache counters. FIFO counts are kernel receipts, not CPU memory-operation counts.
Architecture & data flow
Follow messages between simulated modules, then inspect the exact queues.
A FIFO is a message buffer between modules: first in, first out. Each connection has its own buffer; a diagram link can group several connections.
Select a module group or a directed link to explore its queues. Link counts bundle separate FIFOs; they are not one shared buffer.
All queues
This is a simulator object graph, not a physical CPU floorplan.
Memory request flow SIMULATED CYCLES
Recorded request and response activity.
*Retries count only captured cycles. Missing history is not inferred from host spans.
Cache line & shared memory SIMULATED STATE
| Component | Level | Permission | Dirty responsibility | Slot | Directory sharers / owner |
|---|
Recorded line traffic and ownership events
Whole capture, including later events. Select a cycle to inspect the resulting boundary. Initial pre-window history is unavailable.
Resource activity at this boundary
Permissions and dirty responsibility are modeled; memory values are not. Directory metadata may temporarily lead or lag installed copies while acknowledgments travel. These are simulated caches, not the host CPU caches.
Host execution HOST TIME · µs
Which owners ran on each worker. This is computer time, not simulated CPU cycles.
Phase detail gives each phase its own time scale. Full timing preserves the gaps between phases.
Captured tasks
In start-time orderNo host task observations yet.
Task completion order does not define architectural FIFO order. No scheduler internals or hardware counters are inferred.